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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16303-3E
32-bit RISC Microcontroller
CMOS
FR30 Series MB91121
MB91121
s DESCRIPTION
The MB91121 is a microcontroller with a 32-bit RISC CPU (FR family *) as the core, incorporating a variety of I/O resources, a bus control facility, and a multiplier-accumulator (simplified DSP) with internal program RAM for built-in control applications which require advanced, high-speed CPU processing. While being based on external bus access for supporting a vast address space accessed by the 32-bit CPU, it contains 1 K bytes of instruction cache memory and 4 K bytes of RAM (8 K bytes when the DSP is not used) for speeding up the execution of instructions by the CPU. In this way, the device is designed for built-in applications which require high performance and processing power of the CPU, such as digital camera, navigation system, and high-performance FAX, and printer controls. * : FR Family stands for FUJITSU RISC controller.
s FEATURES
1. FR CPU
* * * * * 32-bit RISC, load/store architecture, 5-stage pipeline Operating clock frequency : Internal 50 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz) General purpose registers : 32 bits x 16 16-bit fixed length instructions (basic instructions) , 1 instruction/1 cycle Memory to memory transfer, bit processing, barrel shifter processing : Optimized for embedded applications (Continued) 120-pin plastic LQFP
s PACKAGE
(FPT-120P-M21)
MB91121
(Continued) * Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems supporting high level languages * Register interlock functions, efficient assembly language coding * Branch instructions with delay slots : Reduced overhead time in branch executions * Internal multiplier/supported at instruction level Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles * Interrupt (push PC and PS) : 6 cycles, 16 priority levels
2. Bus interface
Clock doubler : Internal 50 MHz, external bus 25 MHz operation 25-bit address bus (32 Mbytes memory space) 8/16-bit data bus Basic external bus cycle : 2 clock cycles Chip select outputs for setting down to a minimum memory block size of 64 Kbytes : 6 Interface supported for various memory technologies DRAM interface (area 4 and 5) * Automatic wait cycle insertion : Flexible setting, from 0 to 7 for each area * Unused data/address pins can be configured as input/output ports. * Little endian mode supported (Select 1 area from area 1 to 5) * * * * * *
3. DRAM interface
* * * * * 2 banks independent control (area 4 and 5) Double CAS DRAM (Normal DRAM I/F) /Single CAS DRAM/Hyper DRAM Basic bus cycle : Normally 5 cycles, 2-cycle access possible in high-speed page mode Programmable waveform : Automatic 1-cycle wait insertion to RAS and CAS cycles DRAM refresh CBR refresh (interval time configurable by 6-bit timer) Self-refresh mode * Supports 8/9/10/12-bit column address width * 2CAS/1WE, 2WE/1CAS selective
4. DSP Macros (Simplified DSP)
High-speed multiply-accumulate operation (1 machine cycle) Data format : 16-bit fixed-point (16 x 16 + 40 bits) Instruction area : 256 words x 16 bits Data area : 64 words x 16 bits x 1 set, 1024 words x 16 bits x 2 sets (banks) Capable of rounding and saturation processing Number of terms in addition : Up to 32 terms Instructions : MAC, STR, and JMP instructions Delay processing : Capable of free transfer within 32 words Fixed-point system : Capable of selection from among Q12 to Q15 Program execution control : Capable of externally selecting eight calculation programs Variable monitoring : Capable of monitoring calculation results of up to 4 words without stopping the program * Efficient data variable areas : Two banks of data variable areas provided, enabling the CPU to execute a DSP calculation program using one bank while accessing a data variable in the other. * * * * * * * * * * *
5. Cache memory
* 1 K-byte instruction cache * 2-way set-associative configuration * 32 blocks/way, 4 entries (4 words) /block 2
MB91121
(Continued) * Lock feature: Keeping a specific program code resident in the cache
6. DMAC (DMA Controller)
* * * * * * * * * * * * * * * * * * 9. 8 channels Transfer incident/external pins/UART interrupt requests/DSP Macros/Software start Transfer sequence : Step transfer/block transfer/burst transfer/continuous transfer Transfer data length : 8 bits/16 bits/32 bits selective Interrupt request enables temporary stop operation 3 independent channels Full-duplex double buffer Data length : 7 bits to 9 bits (non-parity) , 6 bits to 8 bits (parity) Asynchronous (start-stop system) , CLK-synchronized communication selective Multi-processor mode Internal 16-bit timer (U-TIMER) operating as a proprietary baud rate generator : Generates any given baud rate Use external clock can be used as a transfer clock Error detection : Parity, frame, overrun 10-bit resolution, 8 channels Successive approximation type : Conversion time of 5.6 s at 25 MHz Internal sample and hold circuit Conversion mode : Single conversion/scanning conversion/repeated conversion selective Start : Software/external trigger/internal timer selective
7. UART
8. A/D converter (successive approximation conversion type)
Reload timer * 16-bit timer : 3 channels * Internal clock : 2 clock cycle resolution, divide by 2/8/32 selective * 16-bit timer : 3 channels (U-TIMER) * PWM timer : 4 channels * Watchdog timer : 1 channel
10. Other interval timers
11. Bit search module
* First bit transition "1" or "0" from MSB can be detected in 1 cycle
12. Interrupt controller
* External interrupt input : Non-maskable interrupt (NMI) , normal interrupt x 8 (INT0 to INT7) * Internal interrupt incident : UART, DMA controller (DMAC) , A/D converter, U-TIMER, delayed interrupt module and DSP Macros * Priority levels of interrupts are programmable except for non-maskable interrupt (in 16 steps) .
Others
1. Reset cause
* Power-on reset/watchdog timer/software reset/external reset
2. Low-power consumption mode
* Sleep mode/stop mode
3. Clock control
* Gear function : Operating clocks for CPU and peripherals are independently selective Gear clock can be selected from 1/1, 1/2, 1/4 and 1/8 (or 1/2, 1/4, 1/8 and 1/16) However, operating frequency for peripherals is less than 25 MHz. 3
MB91121
(Continued)
4. Packages : LQFP-120 5. CMOS technology (0.35 m) 6. Power supply voltage 3.3 V 0.3 V
4
MB91121
s PIN ASSIGNMENT
(TOP VIEW)
RAS1/PB4 DW0/PB3 CSOH/PB2 CSOL/PB1 RAS0/PB0 VCC X0 X1 VSS PI1/EOP2/ATG PI0/DACK2 PE7/DREQ2 PE6/EOP1 PE5/DACK1 PE4/DREQ1 PE3/EOP0 PE2/DACK0 PE1/DREQ0 PE0/SC2 PF7/SO2 PF6/SI2 PF5/SC1 PF4/SO1 PF3/SI1 PF2/SC0 PF1/SO0 VSS PF0/SI0 PG7/INT7/TRG3 PG6/INT6/TRG2 PB5/CS1L PB6/CS1H PB7/DW1 VCC CS0 PA1/CS1 PA2/CS2 PA3/CS3 PA4/CS4 PA5/CS5 PA6/CLK NMI MD3 RST VSS MD0 MD1 MD2 P80/RDY P81/BGRNT P82/BRQ RD WR0 P85/WR1 P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
P26/D22 P27/D23 D24 D25 D26 D27 D28 D29 D30 D31 VSS A00 A01 A02 A03 A04 A05 A06 A07 VCC A08 A09 A10 A11 A12 A13 A14 A15 VSS P60/A16
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
PG5/INT5/TRG1 PG4/INT4/TRG0 PG3/INT3 PG2/INT2 PG1/INT1 PG0/INT0 VCC PH7/OCPA3 PH6/OCPA2 PH5/OCPA1 PH4/OCPA0 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 AVSS/AVRL AVRH AVCC A24 A23/P67 A22/P66 A21/P65 A20/P64 A19/P63 A18/P62 A17/P61
(FPT-120P-M21)
5
MB91121
s PIN DESCRIPTION
Pin no. 1 2 3 4 5 6 7 8 9 Pin name A17/P61 A18/P62 A19/P63 A20/P64 A21/P65 A22/P66 A23/P67 A24 AVCC Circuit type Function
F
Bits 16 to 23 for the external address bus. When not used for the address bus, these pins serve as ports (P60 to P67) .
M
Bit 24 for the external address bus A/D converter VCC power supply A/D converter reference voltage (high potential side) The VCC pin must be applied with voltage equal to or higher than the voltage at this pin (AVRH) when the AVRH pin is turned on or off. A/D converter VSS power supply or reference voltage (low potential side) [AN0 to AN7] A/D converter analog input. This function is enabled with the AIC register set for the analog input. [OCPA0 to OCPA3] PWM timer output. This function is enabled with the PWM timer output flag set to "Enabled". [PH4 to PH7] General-purpose I/O port [INT0 to INT7] External interrupt request input Since these inputs are used during their respective input operations, the output by the other function must remain off unless used intentionally.
10
AVRH
11 12 to 19
AVSS/AVRL AN0 to AN7 OCPA0/PH4 OCPA1/PH5 OCPA2/PH6 OCPA3/PH7 INT0/PG0 INT1/PG1 INT2/PG2 INT3/PG3 INT4/PG4/TRG0 INT5/PG5/TRG1 INT6/PG6/TRG2 INT7/PG7/TRG3
N
20 to 23
F
25 to 32
F
[TRG0 to TRG3] PWM timer external trigger input
[PG0 to PG7] General-purpose I/O port [SI0] UART0 data input. Since this input is used whenever UART0 is in input operation, the output by the other function must remain off unless used intentionally. [PF0] General-purpose I/O port [SO0] UART0 data output. This function is enabled with the UART0 data output flag set to "Enabled". [PF1] General-purpose I/O port. This function is enabled with the UART0 data output flag set to "Disabled". [SC0] UART0 clock input/output. The clock output is enabled with the UART0 clock output flag set to "Enabled". [PF2] General-purpose I/O port. This function is enabled with the UART0 clock output flag set to "Disabled".
33
SI0/PF0
F
35
SO0/PF1
F
36
SC0/PF2
F
(Continued)
6
MB91121
(Continued) Pin no.
Pin name Circuit type Function [SI1] UART1 data input. Since this input is used whenever UART1 is in input operation, the output by the other function must remain off unless used intentionally. [PF3] General-purpose I/O port [SO1] UART1 data output. This function is enabled with the UART1 data output flag set to "Enabled". [PF4] General-purpose I/O port. This function is enabled with the UART1 data output flag set to "Disabled". [SC1] UART1 clock input/output. The clock output is enabled with the UART1 clock output flag set to "Enabled". [PF5] General-purpose I/O port. This function is enabled with the UART1 clock output flag set to "Disabled". [SI2] UART2 data input. Since this input is used whenever UART2 is in input operation, the output by the other function must remain off unless used intentionally. [PF6] General-purpose I/O port [SO2] UART2 data output. This function is enabled with the UART2 data output flag set to "Enabled". [PF7] General-purpose I/O port. This function is enabled with the UART2 data output flag set to "Disabled". [SC2] UART2 clock input/output. The clock output is enabled with the UART2 clock output flag set to "Enabled". [PE0] General-purpose I/O port. This function is enabled with the UART2 clock output flag set to "Disabled". [DREQ0] DMA external transfer request input (ch0) . Since this input is used whenever the DMA external transfer request has been selected as a DMA transfer trigger event, the output by the other function must remain off unless used intentionally. [PE1] General-purpose I/O port [DACK0] DMAC external transfer request acknowledge output (ch0) . This function is enabled with the DMAC transfer request acknowledge output flag set to "Enabled". [PE2] General-purpose I/O port. This function is enabled with the DMAC transfer request acknowledge output flag or DACK0 output flag set to "Disabled". [EOP0] DMAC EOP output (ch0) . This function is enabled with the EOP output flag set to "Enabled". [PE3] General-purpose I/O port [DREQ1] DMA external transfer request input (ch1) . Since this input is used whenever the DMA external transfer request has been selected as a DMA transfer trigger event, the output by the other function must remain off unless used intentionally. [PE4] General-purpose I/O port
37
SI1/PF3
F
38
SO1/PF4
F
39
SC1/PF5
F
40
SI2/PF6
F
41
SO2/PF7
F
42
SC2/PE0
F
43
DREQ0/PE1
F
44
DACK0/PE2
F
45
EOP0/PE3
F
46
DREQ1/PE4
F
(Continued)
7
MB91121
(Continued) Pin no.
Pin name Circuit type Function [DACK1] DMAC external transfer request acknowledge output (ch1) . This function is enabled with the DMAC transfer request acknowledge output flag set to "Enabled". [PE5] General-purpose I/O port. This function is enabled with the DMAC transfer request acknowledge output flag or DACK0 output flag set to "Disabled". [EOP1] DMAC EOP output (ch1) . This function is enabled with the EOP output flag set to "Enabled". [PE6] General-purpose I/O port [DREQ2] DMA external transfer request input (ch2) . Since this input is used whenever the DMA external transfer request has been selected as a DMA transfer trigger event, the output by the other function must remain off unless used intentionally. [PE7] General-purpose I/O port [DACK2] DMAC external transfer request acknowledge output (ch2) . This function is enabled with the DMAC transfer request acknowledge output flag set to "Enabled". [PI0] General-purpose I/O port. This function is enabled with the DMAC transfer request acknowledge output flag or DACK0 output flag set to "Disabled". [EOP2] DMAC EOP output (ch2) . This function is enabled with the EOP output flag set to "Enabled". [ATG] A/D converter external trigger input. Since this input is used whenever the A/D converter external trigger signal has been selected as an A/D trigger event, the output by the other function must remain off unless used intentionally. [PI1] General-purpose I/O port. This function is enabled with the DMAC transfer termination signal output flag set to "Disabled". 53 54 56 57 58 59 60 61 62 63 65 X1 X0 RAS0/PB0 CSOL/PB1 CSOH/PB2 DW0/PB3 RAS1/PB4 CS1L/PB5 CS1H/PB6 DW1/PB7 CS0 A Clock (oscillation) output. Clock (oscillation) input. RAS output of DRAM bank 0 CASL output of DRAM bank 0 CASH output of DRAM bank 0 WE output of DRAM bank 0 (Low active) RAS output of DRAM bank 1 [PB0 to PB3] Can serve as a port when not used for signal output. CASL output of DRAM bank 1 CASH output of DRAM bank 1 WE output of DRAM bank 1 (Low active) [PB5 to PB7] Can serve as a port when not used for signal output. M Chip select 0 output (Low active) .
47
DACK1/PE5
F
48
EOP1/PE6
F
49
DREQ2/PE7
F
50
DACK2/PI0
F
51
EOP2/ATG/PI1
F
F
F
(Continued)
8
MB91121
(Continued)
Pin no. 66 67 68 69 70 Pin name CS1/PA1 CS2/PA2 CS3/PA3 CS4/PA4 CS5/PA5 Circuit type Function Chip select 1 output (Low active) . Chip select 2 output (Low active) . Chip select 3 output (Low active) . Chip select 4 output (Low active) . Chip select 5 output (Low active) . [PA1 to PA5] Can serve as a port when not used for signal output. F H G B G System clock output. This pin outputs the same clock frequency as the external bus operating frequency. [PA6] Can serve as a port when not used for signal output. 72 73 74 76 77 78 79 NMI MD3 RST MD0 MD1 MD2 RDY/P80 NMI (Non Maskable Interrupt) input (Low active) . Mode pin 3. Connect this pin directly to the VCC or VSS pin. External reset input. Mode pins 0 to 2. These pins are set to MCU basic operation modes. Connect this pin directly to the VCC or VSS pin. External ready signal input. This pin inputs 0 when the bus cycle being executed is not completed. It can serve as a port when not used for that input. External bus release request acknowledge output. This pin outputs the L signal when the eternal bus has been released. The pin can serve as a port when not used for that output. External bus release request input. Input 1 to this pin to release the external bus. The pin can serve as a port when not used for that input. External bus read strobe. External bus write strobe. The control signals and data bus byte locations have the following relationships. 16-bit bus width 84 WR1/P85 F D31 to D24 D23 to D16 WR0 WR1 8-bit bus width WR0 (Usable as port)
F
71
CLK/PA6
C
80
BGRNT/P81
F
81 82 83
BRQ/P82 RD WR0
C M M
Note : WR1 remains in the Hi-Z state during a reset. For use with a 16-bit bus width, add an external pull-up resistor. 85 86 87 88 89 90 91 92 D16/P20 D17/P21 D18/P22 D19/P23 D20/P24 D21/P25 D22/P26 D23/P27
C
External data bus bits 16 to 23. These pins can be used as ports (P20 to P27) when the external bus width has been set to 8 bits.
(Continued)
9
MB91121
(Continued)
Pin no. 93 94 95 96 97 98 99 100 102 103 104 105 106 107 108 109 111 112 113 114 115 116 117 118 120 24 55 64 110 34 52 75 101 119 Pin name D24 D25 D26 D27 D28 D29 D30 D31 A00 A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16/P60 Circuit type Function
C
External data bus bits 24 to 31.
F
External address bus bits 00 to 15.
External address bus bit 16. This pin can serve as a port (P60) when not used as the address bus.
VCC
Power supply pin for digital circuit.
VSS
Earth level for digital circuit.
Note : In most of the above pins, I/O port and resource I/O are multiplexed xxxx/Pxx. In case of conflict between output of I/O port and resource I/O, priority is always given to the output of resource I/O.
10
MB91121
s DRAM CONTROL PIN
Pin name RAS0 RAS1 CS0L CS0H CS1L CS1H DW0 DW1 Data bus 16-bit mode 2CAS/1WR mode Area 4 RAS Area 5 RAS Area 4 CASL Area 4 CASH Area 5 CASL Area 5 CASH Area 4 WE Area 5 WE 1CAS/2WR mode Area 4 RAS Area 5 RAS Area 4 CAS Area 4 WEL Area 5 CAS Area 5 WEL Area 4 WEH Area 5 WEH Data bus 8-bit mode Area 4 RAS Area 5 RAS Area 4 CAS Area 4 CAS Area 5 CAS Area 5 CAS Area 4 WE Area 5 WE Remarks Correspondence of "L" "H" to lower address 1 bit (A0) in data bus 16-bit mode "L" : "0" "H" : "1" CASL : CAS which A0 corresponds to "0" area CASH : CAS which A0 corresponds to "1" area WEL : WE which A0 corresponds to "0" area WEH : WE which A0 corresponds to "1" area
11
MB91121
s I/O CIRCUIT TYPE
Circuit Type Circuit Remarks
X1 Clock input
A
X0
* Oscillation feedback resistance 1 M approx.
Standby control signal
VCC P-channel type Tr
B
Diffuse resistor VSS
N-channel type Tr
* CMOS level Hysteresis input Without standby control With pull-up resistance
Digital input
Digital output
Digital output
C
Digital input STANDBY CONTROL
* CMOS level I/O With standby control
N
* Analog input
Analog input
(Continued)
12
MB91121
(Continued)
Circuit Type Circuit Remarks
Digital output
Digital output
F
Digital input STANDBY CONTROL
* CMOS level output * CMOS level Hysteresis input With standby control
G
* CMOS level input Without standby control
Digital input
H
* CMOS level Hysteresis input Without standby control
Digital input
Digital output
M
Digital output
* CMOS level output
13
MB91121
s HANDLING DEVICES
* Preventing Latchup In CMOS ICs, applying voltage higher than VCC or lower than VSS to input/output pin or applying voltage over rating across VCC and VSS may cause latchup. This phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the device. Make sure to prevent the voltage from exceeding the maximum rating. Take care that the analog power supply (AVCC AVR) and the analog input do not exceed the digital power supply (VCC) when the analog power supply turned on or off. * Treatment of Unused Pins Unused pins left open may cause malfunctions. Make sure to connect them to pull-up or pull-down resistors. * External Reset Input It takes at least 5 machine cycle to input "L" level to the RST pin and to ensure inner reset operation properly. * Remarks for External Clock Operation When external clock is selected, supply it to X0 pin generally, and simultaneously the opposite phase clock to X0 must be supplied to X1 pin. However, in this case the stop mode must not be used (because X1 pin stops at "H" output in stop mode) . And can be used to supply only to X0 pin with 5 V power supply at 12.5 MHz and less than. * Using an external clock
X0 X1 MB91121
Using an external clock (normal) Note: Can not be used stop mode (oscillation stop mode).
X0 OPEN X1 MB91121
Using an external clock (can be used at 12.5 MHz and less than.)
* Power Supply Pins When there are several VCC and VSS pins, each of them is equipotentially connected to its counterpart inside of the device, minimizing the risk of malfunctions such as latch up. To further reduce the risk of malfunctions, to prevent EMI radiation, to prevent strobe signal malfunction resulting from creeping-up of ground level and to observe the total output current standard, connect all VCC and VSS pins to the power supply or GND. It is preferred to connect VCC and VSS of MB91121 to power supply with minimal impedance possible. It is also recommended to connect a ceramic capacitor as a bypass capacitor of about 0.1 F between VCC and VSS at a position as close as possible to MB91121. 14
MB91121
* Crystal Oscillator Circuit Noises around X0 and X1 pins may cause malfunctions of MB91121. In designing the PC board, layout X0, X1 and crystal oscillator (or ceramic oscillator) and bypass capacitor for grounding as close as possible. It is strongly recommended to design PC board so that X1 and X0 pins are surrounded by grounding area for stable operation. * Treatment of N.C. Pins Make sure to leave N.C. pins open. * Mode Setting Pins (MD0 to MD3) Connect mode setting pins (MD0 to MD3) directly to VCC or VSS. Arrange each mode setting pin and VCC or VSS patterns on the printed circuit board as close as possible and make the impedance between them minimal to prevent mistaken entrance to the test mode caused by noises. * Turning on the Power Supply When turning on the power supply, never fail to start from setting the RST pin to "L" level. And after the power supply voltage goes to VCC level, at least after ensuring the time for 5 machine cycle, then set to "H" level. * Pin Condition at Turning on the Power Supply The pin condition at turning on the power supply is unstable. The circuit starts being initialized after turning on the power supply and then starting oscillation and then the operation becomes stable. * Source Oscillation Input at Turning on the Power Supply At turning on the power supply, never fail to input the clock before cancellation of the oscillation stabilizing waiting. * The device contains registers which are initialized only at a power-on reset. When it is expected to initialize them, recycle the power to execute a power-on reset. * Even when the A/D converter is not used, make the connections : AVCC = VCC, AVSS = VSS. * Caution on operations during PLL clock mode If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed.
15
MB91121
s BLOCK DIAGRAM
FR CPU
I -bus (16 bit)
RAM (4 KB)
DREQ0 to DREQ2 DACK0 to DACK2 EOP0 to EOP2
3 3 3
D -bus (32 bit)
Bit Search Module
Instruction Cache (1 KB)
DMAC (8 ch)
Bus Converter (HarvardPrinceton) 16 25 2
DSP macro (Embedded RAM 4 )
Bus Converter (32 bit 16 bit)
Bus Controller 6
X0 X1 RST
D16 to D31 A00 to A24 RDY WR0 to WR1 RDY CLK CS0 to CS5 BRQ BGRNT
Clock Control Unit (Watct Dog Timer) RAS0 RAS1 CS0L CS0H CS1L CS1H DW0 DW1
C-bus (32 bit) R -bus (16 bit)
INT0 to INT7 NMI
8
Interrupt Control Unit
DRAM Controller
AN0 to AN7 AVCC AVRH AVSS /AVRL
8 10 bit A/D Converter (8 ch)
Port 0 to Port B
Reload Timer (3 ch)
STRG Soft DMA Start Circuit Port
3 UART (3 ch) with Baud Rate Timer 3 3 SI0 to SI2 SO0 to SO2 SC0 to SC2
PWM Timer (4 ch)
4 4
OCPA0 to OCPA3 TRG0 to TRG3
Note : Pins are display for functions (Actually some pins are multiplexer) . When using REALOS, time control should be done by using external interrupt or inner timer. 16
MB91121
s CPU CORE
1. Memory Space
The FR family has a logical address space of 4 Gbytes (232 bytes) and the CPU linearly accesses the memory space. * Memory space External ROM/external bus mode 0000 0000H I/O 0000 0400H I/O 0000 0800H Access inhibited 0000 1000H Embedded RAM 4 KB 0000 2000H Y-RAM1 0000 2800H Y-RAM1 0000 3000H Access inhibited 0000 F000H DSP Macros 0000 F300H Access inhibited 0001 0000H External area FFFF FFFFH Usable as RAM when DSP Macros is not used. Usable as RAM in the DSP Macros YBANK unused mode. Direct addressing area See "s I/O MAP"
* Direct addressing area The following areas on the memory space are assigned to direct addressing area for I/O. In these areas, an address can be specified in a direct operand of a code. Direct areas consist of the following areas dependent on accessible data sizes. Byte data access : 000H to 0FFH Half word data access : 000H to 1FFH Word data access : 000H to 3FFH
17
MB91121
2. Registers
The FR family has two types of registers; dedicated registers embedded on the CPU and general-purpose registers on memory. * Dedicated registers Program counter (PC) Program status (PS) Table base register (TBR)
: 32-bit length, indicates the location of the instruction to be executed. : 32-bit length, register for storing register pointer or condition codes : Holds top address of vector table used in EIT (Exceptional/Interrupt/Trap) processing. Return pointer (RP) : Holds address to resume operation after returning from a subroutine. System stack pointer (SSP) : Indicates system stack space. User's stack pointer (USP) : Indicates user's stack space. Multiplication/division result register (MDH/MDL) : 32-bit length, register for multiplication/division
Initial value Program counter Program status Table base register Return pointer System stack pointer User's stack pointer 0 0 0 F FC0 0H XXXX XXXXH Indeterminate 0 0 0 0 0 0 0 0H XXXX XXXXH Indeterminate XXXX XXXXH Indeterminate Multiplication/division result register MDL XXXX XXXXH Indeterminate XXXX XXXXH Indeterminate
32 bit PC PS TBR RP SSP USP MDH
* Program status (PS) The PS register is for holding program status and consists of a condition code register (CCR) , a system condition code register (SCR) and a interrupt level mask register (ILM) .
31 PS 20 19 18 17 16 10 D1 9 D0 8 T 7 6 5 S 4 I 3 N 2 Z 1 V 0 C
ILM4 ILM3 ILM2 ILM1 ILM0
ILM
SCR
CCR
18
MB91121
* Condition code register (CCR) S-flag : Specifies a stack pointer used as R15. I-flag : Controls user interrupt request enable/disable. N-flag : Indicates sign bit when division result is assumed to be in the 2's complement format. Z-flag : Indicates whether or not the result of division was "0". V-flag : Assumes the operand used in calculation in the 2's complement format and indicates whether or not overflow has occurred. C-flag : Indicates if a carry or borrow from the MSB has occurred. * System condition code register (SCR) T-flag : Specifies whether or not to enable step trace trap. * Interrupt level mask register (ILM) ILM4 to ILM0 : Register for holding interrupt level mask value. The value held by this register is used as a level mask. When an interrupt request issued to the CPU is higher than the level held by ILM, the interrupt request is accepted. ILM4 ILM3 ILM2 ILM1 ILM0 Interrupt level High-low 0 0 0 : : 0 1 0 : : 1 1 1 1 1 0 0 0 0 0 : : 15 : : 31 Low High
19
MB91121
s GENERAL-PURPOSE REGISTERS
R0 to R15 are general-purpose registers embedded on the CPU. These registers functions as an accumulator and a memory access pointer (field for indicating address) . * Register bank structure
32 bits R0 R1 Initial value XXXX XXXXH
R12 R13 R14 R15
AC (Accumulator) FP (Frame Pointer) SP (Stack Pointer)
XXXX XXXXH 0 0 0 0 0 0 0 0H
Of the above 16 registers, following registers have special functions. To support the special functions, part of the instruction set has been sophisticated to have enhanced functions. R13 : Virtual accumulator (AC) R14 : Frame pointer (FP) R15 : Stack pointer (SP) Upon reset, values in R0 to R14 are not fixed. Value in R15 is initialized to be 0000 0000H (SSP value) .
20
MB91121
s SETTING MODE
1. Pin
* Mode setting pins and modes Mode setting pins Mode name MD3 MD2 MD1 MD0 1 1 1 1 1 0 0 0 0 0 1 0 0 1 1 0 1 0 1 External vector mode 0 External vector mode 1 Internal vector mode Reset vector access area External External Internal External data bus width 8 bits 16 bits (Mode register) Bus mode External ROM/external bus mode Inhibited Single-chip mode* Inhibited Inhibited
* : MB91121 does not support single-chip mode.
2. Registers
* Mode setting registers (MODR) and modes
Address 0000 07FFH M1 M0 * * * * * *
Initial value XXXX XXXXB
Access W
Bus mode setting bit
W : Write only X : Indeterminate * : Always write "0" except for M1 and M0.
* Bus mode setting bits and functions M1 M0 0 0 1 1 0 1 0 1 Single-chip mode
Functions
Note
Internal ROM/external bus mode External ROM/external bus mode Inhibited
Note : Because of without internal ROM, MB91121 allows "10B" setting value only.
21
MB91121
s I/O MAP
Address 0000H 0001H 0002H to 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH to 0011H 0012H 0013H 0014H 0015H 0016H 0017H to 001BH 001CH 001DH 001EH 001FH 0020H 0021H 0022H 0023H 0024H 0025H 0026H 0027H SSR0 SIDR0/SODR0 SCR0 SMR0 SSR1 SIDR1/SODR1 SCR1 SMR1 SSR2 SIDR2/SODR2 SCR2 SMR2 Serial status register 0 Serial input register 0/serial output register 0 Serial control register 0 Serial mode register 0 Serial status register 1 Serial input register 1/serial output register 1 Serial control register 1 Serial mode register 1 Serial status register 2 Serial input register 2/serial output register 2 Serial control register 2 Serial mode register 2 PDRE PDRF PDRG PDRH PDRI Port E data register Port F data register Port G data register Port H data register Port I data register (Vacancy) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 1 - 0 0B XXXXXXXXB 0 0 0 0 0 1 0 0B 0 0 - - 0 - 0 0B 0 0 0 0 1 - 0 0B XXXXXXXXB 0 0 0 0 0 1 0 0B 0 0 - - 0 - 0 0B 0 0 0 0 1 - 0 0B XXXXXXXXB 0 0 0 0 0 1 0 0B 0 0 - - 0 - 0 0B PDR8 Port 8 data register (Vacancy) R/W R/W R/W R/W R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXX - - - -B - - - - - - XXB PDRB PDRA Port B data register Port A data register (Vacancy) R/W - -X - -XXXB PDR6 Port 6 data register (Vacancy) R/W R/W XXXXXXXXB -XXXXXX -B PDR2 Port 2 data register (Vacancy) R/W XXXXXXXXB Register name (abbreviated) Register name (Vacancy) R/W XXXXXXXXB Read/write Initial value
(Continued)
22
MB91121
Address 0028H 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH 0040H 0041H 0042H 0043H 0044H to 004FH 0050H 0051H to 0077H STRG Soft DMA Start (Vacancy) TMCSR2 TMCSR1 ADCR ADCS TMRLR2 TMR2 TMCSR0 TMRLR1 TMR1 Register name (abbreviated) TMRLR0 TMR0 Register name 16-bit reload register ch. 0 16-bit timer register ch. 0 (Vacancy) 16-bit reload timer control status register ch. 0 16-bit reload register ch. 1 16-bit timer register ch. 1 (Vacancy) 16-bit reload timer control status register ch. 1 A/D converter data register A/D converter control status register 16-bit reload register ch. 2 16-bit timer register ch. 2 (Vacancy) 16-bit reload timer control status register ch. 2 R/W - - - - 0 0 0 0B 0 0 0 0 0 0 0 0B R/W R R/W W R - - - - 0 0 0 0B 0 0 0 0 0 0 0 0B - - - - - - XXB XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB R/W W R - - - - 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Read/write W R Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
(Vacancy) R/W - - - - - - 0 0B
(Continued)
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MB91121
Address 0078H 0079H 007AH 007BH 007CH 007DH 007EH 007FH 0080H 0081H 0082H 0083H 0084H to 0093H 0094H 0095H 0096H to 0097H 0098H 0099H 009AH to 00D1H 00D2H 00D3H 00D4H 00D5H 00D6H 00D7H to 00DBH 00DCH 00DDH 00DEH 00DFH GCN2 GCN1 DDRE DDRF DDRG DDRH DDRI ELVR EIRR ENIR Interrupt enable register (Vacancy) UTIMC2 UTIMC1 UTIM2/UTIMR2 UTIMC0 UTIM1/UTIMR1 Register name (abbreviated) UTIM0/UTIMR0 Register name U-TIMER register ch. 0/reload register ch. 0 (Vacancy) U-TIMER control register ch. 0 U-TIMER register ch. 1/reload register ch. 1 (Vacancy) U-TIMER control register ch. 1 U-TIMER register ch. 2/reload register ch. 2 (Vacancy) U-TIMER control register ch. 2 (Vacancy) External interrupt cause register R/W R/W 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B R/W 0 - - 0 0 0 0 1B R/W R/W 0 - - 0 0 0 0 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B R/W R/W 0 - - 0 0 0 0 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B Read/write R/W Initial value 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
External interrupt request level setting register
R/W
0 0 0 0 0 0 0 0B
(Vacancy) Port E data direction register Port F data direction register Port G data direction register Port H data direction register Port I data direction register (Vacancy) 0 0 1 1 0 0 1 0B 0 0 0 1 0 0 0 0B 0 0 0 0 0 0 0 0B W W W W W 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 - - - -B - - - - - - 0 0B
General control register 1 (Vacancy) General control register 2
R/W
R/W
(Continued)
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MB91121
Address 00E0H 00E1H 00E2H 00E3H 00E4H 00E5H 00E6H 00E7H 00E8H 00E9H 00EAH 00EBH 00ECH 00EDH 00EEH 00EFH 00F0H 00F1H 00F2H 00F3H 00F4H 00F5H 00F6H 00F7H 00F8H 00F9H 00FAH 00FBH 00FCH 00FDH 00FEH 00FFH 0100H to 01FFH Register name (abbreviated) PTMR0 PCSR0 PDUT0 PCNH0 PCNL0 PTMR1 PCSR1 PDUT1 PCNH1 PCNL1 PTMR2 PCSR2 PDUT2 PCNH2 PCNL2 PTMR3 PCSR3 PDUT3 PCNH3 PCNL3 Register name PWM timer register PWM cycle setting register PWM duty setting register PWM control status register H PWM control status register L PWM timer register PWM cycle setting register PWM duty setting register PWM control status register H PWM control status register L PWM timer register PWM cycle setting register PWM duty setting register PWM control status register H PWM control status register L PWM timer register PWM cycle setting register PWM duty setting register PWM control status register H PWM control status register L (Vacancy) Read/write R W W R/W R/W R W W R/W R/W R W W R/W R/W R W W R/W R/W Initial value 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 -B 0 0 0 0 0 0 0 0B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 -B 0 0 0 0 0 0 0 0B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 -B 0 0 0 0 0 0 0 0B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 -B 0 0 0 0 0 0 0 0B
(Continued)
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MB91121
Address 0200H 0201H 0202H 0203H 0204H 0205H 0206H 0207H 0208H 0209H 020AH 020BH 020CH to 020FH 0210H 0211H 0212H 0213H 0214H 0215H 0216H 0217H 0218H 0219H 021AH 021BH 021CH 021DH 021EH 021FH 0220H 0221H 0222H 0223H OFSS Y-BANKC OFSD DSP-PC DSP-CSR DSP-LY DSP-OT0 DSP-OT1 DSP-OT2 DSP macro register OFAS STRS OFSC (Vacancy) R/W R/W R/W R/W R/W R/W R R R 0 0 0 0 0 0 0 0B 0 - - 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0 0B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB DSP macro register R/W (Vacancy) - - - - 0 0 0 0B 0 0 0 0 0 0 0 0B - - - - 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 - - - 0B DATCR DMAC pin control register R/W DACSR DMAC control status register R/W DPDP DMAC parameter descriptor pointer R/W Register name (abbreviated) Register name Read/write Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB X0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB XXXX0 0 0 0B XXXX0 0 0 0B XXXX0 0 0 0B
(Continued)
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MB91121
Address 0224H 0225H 0226H to 03E3H 03E4H 03E5H 03E6H 03E7H 03E8H to 03EFH 03F0H 03F1H 03F2H 03F3H 03F4H 03F5H 03F6H 03F7H 03F8H 03F9H 03FAH 03FBH 03FCH 03FDH 03FEH 03FFH 0400H 0401H 0402H 0403H 0404H 0405H 0406H 0407H ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 Interrupt control register 0 Interrupt control register 1 Interrupt control register 2 Interrupt control register 3 Interrupt control register 4 Interrupt control register 5 Interrupt control register 6 Interrupt control register 7 R/W R/W R/W R/W R/W R/W R/W R/W BSRR Bit search module detection result register R BSDC Bit search module transition-detection data register W BSD1 Bit search module 1-detection data register R/W BSD0 Bit search module 0-detection data register W (Vacancy) XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B ICHCR Instruction cache control register R/W Register name (abbreviated) DSP-OT3 Register name DSP macro register Read/write R Initial value XXXXXXXXB XXXXXXXXB
(Vacancy) - - - - - - - -B - - - - - - - -B - - - - - - - -B - - 0 0 0 0 0 0B
(Continued)
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MB91121
Address 0408H 0409H 040AH 040BH 040CH 040DH 040EH 040FH 0410H 0411H 0412H 0413H 0414H 0415H 0416H 0417H 0418H 0419H 041AH 041BH 041CH 041DH 041EH 041FH 0420H to 042EH 042FH 0430H 0431H 0432H to 047FH 0480H 0481H 0482H RSRR/WTCR STCR PDRR Register name (abbreviated) ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 to ICR46 ICR47 DICR HRCL Register name Interrupt control register 8 Interrupt control register 9 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 Interrupt control register 16 Interrupt control register 17 Interrupt control register 18 Interrupt control register 19 Interrupt control register 20 Interrupt control register 21 Interrupt control register 22 Interrupt control register 23 Interrupt control register 24 Interrupt control register 25 Interrupt control register 26 Interrupt control register 27 Interrupt control register 28 Interrupt control register 29 Interrupt control register 30 Interrupt control register 31 Interrupt control register 32 to 46 Interrupt control register 47 Delayed interrupt control register Hold request cancel request level setting register (Vacancy) Reset cause register/ watchdog peripheral control register Standby control register DMA controller request squelch register 1XXXX - 0 0B 0 0 0 1 1 1 - -B - - - - 0 0 0 0B Read/write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - - - - - 0B - - - 1 1 1 1 1B
R/W R/W R/W
(Continued)
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MB91121
Address 0483H 0484H 0485H 0486H 0487H 0488H 0489H to 0600H 0601H 0602H to 0604H 0605H 0606H 0607H 0608H 0609H 060AH 060BH 060CH 060DH 060EH 060FH 0610H 0611H 0612H 0613H 0614H 0615H 0616H 0617H 0618H 0619H 061AH 061BH DDR8 ASR1 AMR1 ASR2 AMR2 ASR3 AMR3 ASR4 AMR4 DDRB DDRA DDR6 DDR2 PCTR PLL control register (Vacancy) Port 2 data direction register (Vacancy) Port 6 data direction register (Vacancy) Port B data direction register Port A data direction register (Vacancy) Port 8 data direction register Area select register 1 Area mask register 1 Area select register 2 Area mask register 2 Area select register 3 Area mask register 3 Area select register 4 Area mask register 4 W W W W W W W W W - - 0 - - 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 1 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 1 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B W W 0 0 0 0 0 0 0 0B - 0 0 0 0 0 0 -B W 0 0 0 0 0 0 0 0B W 0 0 0 0 0 0 0 0B Register name (abbreviated) CTBR GCR WPR Register name Timebase timer clear register Gear control register Watchdog reset occurrence postpone register (Vacancy) R/W 0 0 - - 0 - - -B Read/write W R/W W Initial value XXXXXXXXB 1 1 0 0 1 1 - 1B XXXXXXXXB
(Continued)
29
MB91121
(Continued)
Address 061CH 061DH 061EH 061FH 0620H 0621H 0622H 0623H 0624H 0625H 0626H 0627H 0628H 0629H 062AH 062BH 062CH 062DH 062EH 062FH 0630H to 07FDH 07FEH 07FFH 002000H to 002FFFH 00F000H to 00F07FH 00F100H to 00F2FFH LER MODR Y-RAM (Variable RAM) 4096 byte (Max.) X-RAM (Coefficient RAM) DSP macro RAM 128 byte I-RAM (Instruction RAM) 512 byte Little endian register Mode register EPCR1 DMCR4 DMCR5 Register name (abbreviated) ASR5 AMR5 AMD0 AMD1 AMD32 AMD4 AMD5 DSCR RFCR EPCR0 Register name Area select register 5 Area mask register 5 Area mode register 0 Area mode register 1 Area mode register 32 Area mode register 4 Area mode register 5 DRAM signal control register Refresh control register External pin control register 0 (Vacancy) External pin control register 1 DRAM control register 4 DRAM control register 5 W R/W R/W 1 1 1 1 1 1 1 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 -B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 -B Read/write W W R/W R/W R/W R/W R/W W R/W W Initial value 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - - - 0 0 1 1 1B 0 - - 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 - - 0 0 0 0 0B 0 - - 0 0 0 0 0B 0 0 0 0 0 0 0 0B - -XXXXXXB 0 0 - - - 0 0 0B - - - - 1 1 0 0B - 1 1 1 1 1 1 1B
(Vacancy) W W - - - - - 0 0 0B XXXXXXXXB
Note : Do not use (vacancy) .
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MB91121
s INTERRUPT CAUSES, INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTER ALLOCATIONS
Interrupt causes Reset Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Exception for undefined instruction NMI request External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 UART0 receive complete UART1 receive complete UART2 receive complete UART0 transmit complete UART1 transmit complete UART2 transmit complete DMAC0 (complete, error) DMAC1 (complete, error) DMAC2 (complete, error) DMAC3 (complete, error) DMAC4 (complete, error) DMAC5 (complete, error) DMAC6 (complete, error) Interrupt number Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Hexadecimal 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 Interrupt level Register FH fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 Offset 3F4H 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380H 37CH TBR default address 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H 000FFF80H 000FFF7CH
(Continued)
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MB91121
Interrupt number Decimal 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 Hexadecimal 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 Interrupt level Register ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47 Offset 378H 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H 2FCH 2F8H TBR default address 000FFF78H 000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H 000FFEFCH 000FFEF8H
Interrupt causes DMAC7 (complete, error) A/D converter (successive approximation conversion type) 16-bit reload timer 0 16-bit reload timer 1 16-bit reload timer 2 PWM 0 PWM 1 PWM 2 PWM 3 U-TIMER 0 U-TIMER 1 U-TIMER 2 External interrupt 4 External interrupt 5 External interrupt 6 External interrupt 7 DSP Macros soft interrupt DSP Macros offset interrupt Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Delayed interrupt cause bit Reserved for system (used in REALOS*) Reserved for system (used in REALOS*)
(Continued)
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MB91121
(Continued)
Interrupt causes Interrupt number Decimal 66 to 255 Hexadecimal 42 to FF Interrupt level Register Offset 2F4H to 000H TBR default address 000FFEF4H to 000FFC00H
Used in INT instructions
* : When using in REALOS/FR, interrupt 0x40, 0x41 for system code.
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MB91121
s PERIPHERAL RESOURCES
1. I/O Ports
There are 2 types of I/O port register structure; port data register (PDR2, 6, 8, A, B, E to I) and data direction register (DDR2, 6, 8, A, B, E to I) , where bits PDR2, 6, 8, A, B, E to I and bits DDR2, 6, 8, A, B, E to I corresponds respectively. Each bit on the register corresponds to an external pin. In port registers input/output register of the port configures input/output function of the port, while corresponding bit (pin) configures input/output function in data direction registers. Bit "0" specifies input and "1" specifies output. * For input (DDR = "0") setting; PDR reading operation : reads level of corresponding external pin. PDR writing operation : writes set value to PDR. * For output (DDR = "1") setting; PDR reading operation : reads PDR value. PDR writing operation : outputs PDR value to corresponding external pin. * Block diagram
Resource input
0
1 PDR read Data bus 0 PDR (Port data register) Resource output 1 Pin
Resource output enable DDR (Data direction register)
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MB91121
* Register explanation * Port Data Register (PDR)
7 PDR2 Address : 000001H PDR6 Address : 000005H PDR8 Address : 00000BH PDRA Address : 000009H PDRB Address : 000008H PDRE Address : 000012H PDRF Address : 000013H PDRG Address : 000014H PDRH Address : 000015H PDRI Address : 000016H P27 7 P67 7 7 7 PB7 7 PE7 7 PF7 7 PG7 7 PH7 7 6 P26 6 P66 6 6 PA6 6 PB6 6 PE6 6 PF6 6 PG6 6 PH6 6 5 P25 5 P65 5 P85 5 PA5 5 PB5 5 PE5 5 PF5 5 PG5 5 PH5 5 4 P24 4 P64 4 4 PA4 4 PB4 4 PE4 4 PF4 4 PG4 4 PH4 4 3 P23 3 P63 3 3 PA3 3 PB3 3 PE3 3 PF3 3 PG3 3 3 2 P22 2 P62 2 P82 2 PA2 2 PB2 2 PE2 2 PF2 2 PG2 2 2 1 P21 1 P61 1 P81 1 PA1 1 PB1 1 PE1 1 PF1 1 PG1 1 1 PI1 0 P20 0 P60 0 P80 0 0 PB0 0 PE0 0 PF0 0 PG0 0 0 PI0 Initial value - - - - - - X XB Access R/W Initial value X X X X - - - -B Access R/W Initial value X X X X X X X XB Access R/W Initial value X X X X X X X XB Access R/W Initial value X X X X X X X XB Access R/W Initial value X X X X X X X XB Access R/W Initial value - X X X X X X -B Access R/W Initial value - - X - - X X XB Access R/W Initial value X X X X X X X XB Access R/W Initial value X X X X X X X XB Access R/W
PDR2 to PDRI is the I/O port input/output data register. The associated register, DDR2 to DDRI, controls the input/output.
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MB91121
* Data Direction Register (DDR)
7 DDR2 Address : 000601H DDR6 Address : 000605H DDR8 Address : 00060BH DDRA Address : 000609H DDRB Address : 000608H DDRE Address : 0000D2H DDRF Address : 0000D3H DDRG Address : 0000D4H DDRH Address : 0000D5H DDRI Address : 0000D6H P27 7 P67 7 7 7 PB7 7 PE7 7 PF7 7 PG7 7 PH7 7 6 P26 6 P66 6 6 PA6 6 PB6 6 PE6 6 PF6 6 PG6 6 PH6 6 5 P25 5 P65 5 P85 5 PA5 5 PB5 5 PE5 5 PF5 5 PG5 5 PH5 5 4 P24 4 P64 4 4 PA4 4 PB4 4 PE4 4 PF4 4 PG4 4 PH4 4 3 P23 3 P63 3 3 PA3 3 PB3 3 PE3 3 PF3 3 PG3 3 3 2 P22 2 P62 2 P82 2 PA2 2 PB2 2 PE2 2 PF2 2 PG2 2 2 1 P21 1 P61 1 P81 1 PA1 1 PB1 1 PE1 1 PF1 1 PG1 1 1 PI1 0 P20 0 P60 0 P80 0 0 PB0 0 PE0 0 PF0 0 PG0 0 0 PI0 Initial value - - - - - - 0 0B Access W Initial value 0 0 0 0 - - - -B Access W Initial value 0 0 0 0 0 0 0 0B Access W Initial value 0 0 0 0 0 0 0 0B Access W Initial value 0 0 0 0 0 0 0 0B Access W Initial value 0 0 0 0 0 0 0 0B Access W Initial value - 0 0 0 0 0 0 -B Access W Initial value - - 0 - - 0 0 0B Access W Initial value 0 0 0 0 0 0 0 0B Access W Initial value 0 0 0 0 0 0 0 0B Access W
DDR2 to DDRI controls the I/O port input/output direction bit by bit. 0 : Input 1 : Output
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MB91121
2. DMA Controller (DMAC)
The DMA controller is a module embedded in FR family devices, and performs DMA (direct memory access) transfer. DMA transfer performed by the DMA controller transfers data without intervention of CPU, contributing to enhanced performance of the system. * * * * * * * 8 channels Mode : single/block transfer, burst transfer and continuous transfer : 3 kinds of transfer Transfer all through the area Max. 65536 of transfer cycles Interrupt function right after the transfer Selectable for address transfer increase/decrease by the software External transfer request input pin, external transfer request accept output pin, external transfer complete output pin three pins for each
* Block diagram
DREQ0 to DREQ2
3
Edge/level detection circuit
3
3 3 Sequencer 8
DACK0 to DACK2 EOP0 to EOP2 Interrupt request
5 Inner resource transfer request
Data buffer
Switcher
DPDP
DATCR
Mode
BLK DEC
BLK
DMACT
INC / DEC
SADR
DADR
Data bus
DACSR
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MB91121
* Registers (DMAC internal registers)
Address bit 31 00000200H 00000201H 00000202H 00000203H 00000204H 00000205H 00000206H 00000207H 00000208H 00000209H 0000020AH 0000020BH ( ) : Access R/W : Readable and writable X : Indeterminate bit 16 DPDP bit 0 X X X X X X X XB X X X X X X X XB X X X X X X X XB X 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B X X X X X X X XB X X X X 0 0 0 0B X X X X 0 0 0 0B X X X X 0 0 0 0B (R/W) Initial value
DACSR
(R/W)
DATCR
(R/W)
* Registers (DMA descriptor)
Address DPDP + 0H DPDP + 0CH bit 31 bit 0 DMA ch.0 Descriptor DMA ch.1 Descriptor
DPDP + 54H
DMA ch.7 Descriptor
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MB91121
3. UART
The UART is a serial I/O port for supporting asynchronous (start-stop system) communication or CLK synchronous communication, and it has the following features. The MB91121 consists of 3 channels of UART. * * * * * * * * Full double double buffer Both a synchronous (start-stop system) communication and CLK synchronous communication are available. Supporting multi-processor mode Perfect programmable baud rate Any baud rate can be set by internal timer (refer to section "4. U-TIMER") . Any baud rate can be set by external clock. Error checking function (parity, framing and overrun) Transfer signal : NRZ code Enable DMA transfer start by interrupt.
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MB91121
* Block diagram
Control signals Receive interrupt (to CPU)
SC (clock) Transmit clock From U-TIMER Clock select circuit Receive clock Transmit interrupt (to CPU)
From external clock SC Receive control circuit Transmit control circuit
SI (receive data)
Start bit detect circuit
Transmit start circuit
Receive bit counter
Transmit bit counter
Receive parity counter
Transmit parity counter
SO (transmit data)
Receive status judge circuit
Receive shifter
Transmit shifter
Receive error generate signal for DMA (to DMAC)
Receive complete SIDR
Transmit start SODR
R-bus
MD1 MD0 SMR register SCR register
CS0 SCKE SOE
PEN P SBL CL A/D REC RXE TXE
SSR register
PE ORE FRE RDRF TDRE RIE TIE
Control signals
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MB91121
* Register configuration
Address bit 15 0000001EH 00000022H 00000026H 0000001FH 00000023H 00000027H 0000001CH 00000020H 00000024H 0000001DH 00000021H 00000002H () R/W X : Access : Readable and writable : Unused : Indeterminate SSR0 SSR1 SSR2 SIDR0/SODR0 SIDR1/SIDR1 SIDR2/SIDR2 SCR0 SCR1 SCR2 SMR0 SMR1 SMR2 bit 8 bit 0
Initial value 0 0 0 0 0 1 0 0B 0 0 0 0 0 1 0 0B 0 0 0 0 0 1 0 0B 0 0 - - 0 - 0 0B 0 0 - - 0 - 0 0B 0 0 - - 0 - 0 0B 0 0 0 0 1 - 0 0B 0 0 0 0 1 - 0 0B 0 0 0 0 1 - 0 0B X X X X X X X XB X X X X X X X XB X X X X X X X XB (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
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MB91121
4. U-TIMER (16-bit Timer for UART Baud Rate Generation)
The U-TIMER is a 16-bit timer for generating UART baud rate. Combination of chip operating frequency and reload value of U-TIMER allows flexible setting of baud rate. The U-TIMER operates as an interval timer by using interrupt issued on counter underflow. The MB91121 has 3 channel U-TIMER embedded on the chip. An interval of up to 216 x can be counted. * Block diagram
bit 15
bit 0
UTIMR (reload register)
Load bit 15 bit 0
UTIM ( U-TIMER register) Underflow (Peripheral clock) Clock Control
f.f.
To UART
* Register configuration
Address bit 15 00000078H 00000079H 0000007CH 0000007DH 00000080H 00000081H 0000007BH 0000007FH 00000083H ( ) : Access R/W : Readable and writable : Unused UTIM0/UTIMR0 bit 0
Initial value 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 - - 0 0 0 0 1B 0 - - 0 0 0 0 1B 0 - - 0 0 0 0 1B (R/W)
UTIM1/UTIMR1
(R/W)
UTIM2/UTIMR2 UTIMC0 UTIMC1 UTIMC2
(R/W)
(R/W) (R/W) (R/W)
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MB91121
5. PWM Timer
The PWM timer can output high accurate PWM waves efficiently. MB91121 has inner 4-channel PWM timers, and has the following features. * Each channel consists of a 16-bit down counter, a 16-bit data resister with a buffer for cycle setting, a 16-bit compare resister with a buffer for duty setting, and a pin controller. * The count clock of a 16-bit down counter can be selected from the following four inner clocks. Inner clock , /4, /16, /64 * The counter value can be initialized "FFFFH" by the resetting or the counter borrow. * PWM output (each channel) * Resister description * Block diagram (general construction)
16-bit reload timer ch.0
TRG input PWM timer ch.0
PWM0
16-bit reload timer ch.1
General control register 1 (cause selection) 4
TRG input PWM timer ch.1
PWM1
General control register 2
TRG input PWM timer ch.2
PWM2
4 External TRG0 to TRG3
TRG input PWM timer ch.3
PWM3
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MB91121
* Block diagram (for one channel)
PCSR
PDUT
Prescaler
1/1 1/4 1 / 16 1 / 64
ck 16-bit down counter Start
Load
cmp
Borrow
PPG mask S Peripheral clock Q
PWM output
R
Reverse bit Interrupt selection Enable TRG input Edge detect Soft trigger
IRQ
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MB91121
* Register configuration
Address bit 15 000000DCH 000000DDH 000000DFH 000000E0H 000000E1H 000000E2H 000000E3H 000000E4H 000000E5H 000000E6H 000000E7H 000000E8H 000000E9H 000000EAH 000000EBH 000000ECH 000000EDH 000000EEH 000000EFH 000000F0H 000000F1H 000000F2H 000000F3H 000000F4H 000000F5H 000000F6H 000000F7H 000000F8H 000000F9H 000000FAH 000000FBH 000000FCH 000000FDH 000000FEH 000000FFH () R/W R W X : Access : Readable and writable : Read only : Write only : Unused : Indeterminate PCNH3 PCNL3 PTMR3 PCSR3 PDUT3 PCNH2 PCNL2 PTMR2 PCSR2 PDUT2 PCNH1 PCNL1 PTMR1 PCSR1 PDUT1 PCNH0 PCNL0 PTMR0 PCSR0 PDUT0 bit 8 GCN1 GCN2 bit 0 0 0 1 1 0 0 1 0B 0 0 0 1 0 0 1 0B 0 0 0 0 0 0 0 0B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB 0 0 0 0 0 0 0 -B 0 0 0 0 0 0 0 0B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB 0 0 0 0 0 0 0 -B 0 0 0 0 0 0 0 0B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB 0 0 0 0 0 0 0 -B 0 0 0 0 0 0 0 0B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB 0 0 0 0 0 0 0 -B 0 0 0 0 0 0 0 0B (R/W) (R/W) (R) (W) (W) (R/W) (R/W) (R) (W) (W) (R/W) (R/W) (R) (W) (W) (R/W) (R/W) (R) (W) (W) (R/W) (R/W) Initial value
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MB91121
6. 16-bit Reload Timer
The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload timer, a prescaler for generating internal count clock and control registers. Internal clock can be selected from 3 types of internal clocks (divided by 2/8/32 of machine clock) . The DMA transfer can be started by the interruption. The MB91121 consists of 3 channels of the 16-bit reload timer. * Block diagram
16 16-bit reload register 8 Reload RELD 16 16-bit down counter UF 2 GATE R-bus CSL1 Clock selector CSL0 2 Retrigger IN CTL. EXCK 3 Prescaler clear MOD2 MOD1 Internal clock MOD0 3 PWM (ch0, ch1) A/D (ch2) TRG CNTE OUTE OUTL OUT CTL. 2 INTE UF IRQ
21 23 25
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MB91121
* Register configuration
Address bit 15 0000002EH 0000002FH 00000036H 00000037H 00000042H 00000043H 0000002AH 0000002BH 00000032H 00000033H 0000003EH 0000003FH 00000028H 00000029H 00000030H 00000031H 0000003CH 0000003DH () R/W R W X : Access : Readable and writable : Read only : Write only : Unused : Indeterminate TMCSR0 TMCSR1 TMCSR2 TMR0 TMR1 TMR2 TMRLR0 TMRLR1 TMRLR2 bit 0
Initial value - - - - 0 0 0 0B 0 0 0 0 0 0 0 0B - - - - 0 0 0 0B 0 0 0 0 0 0 0 0B - - - - 0 0 0 0B 0 0 0 0 0 0 0 0B X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB (R/W) (R/W) (R/W) (R) (R) (R) (W) (W) (W)
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MB91121
7. Bit Search Module
The bit search module detects transitions of data (0 to 1/1 to 0) on the data written on the input registers and returns locations of the transitions. * Block diagram
Input latch
Address decoder
Detection mode
Single-detection data recovery D-bus
Bit search circuit
Search result
* Register configuration
Address bit 31 000003F0H 000003F1H 000003F2H 000003F3H 000003F4H 000003F5H 000003F6H 000003F7H 000003F8H 000003F9H 000003FAH 000003FBH 000003FCH 000003FEH 000003FDH 000003FFH () R/W R W X : Access : Readable and writable : Read only : Write only : Indeterminate bit 16 BSD0 bit 0 X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB (W) Initial value
BSD1
(W)
BSDC
(W)
BSRR
(W)
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MB91121
8. 10-bit A/D Converter (Successive Approximation Conversion Type)
The A/D converter is the module which converts an analog input voltage to a digital value, and it has following features. * * * * Minimum converting time : 5.6 s/ch. (system clock : 25 MHz) Inner sample and hold circuit Resolution : 10 bits Analog input can be selected from 4 channels by program. Single convert mode : 1 channel is selected and converted. Scan convert mode : Converting continuous channels. Maximum 4 channels are programmable. Continuous convert mode : Converting the specified channel repeatedly. Stop convert mode : After converting one channel then stop and wait till next activation synchronising at the beginning of conversion can be peformed. * DMA transfer operation is available by interruption. * Operating factor can be selected from the software, the external trigger (falling edge) , and 16-bit reroad timer (rising edge) .
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MB91121
* Block diagram
AVCC AVR AVSS
Internal voltage generator MPX
AN1 AN2 AN3
Input circuit
AN0
Successive approximation register
Comparator
Sample & hold circuit R-bus Decoder Data register (ADCR) A/D control register (ADCS) ATG Trigger start Timer start Operating clock TIM0 (internal connection) (16-bit reload timer ch.2) (Peripheral clock) Prescaler
* Register configuration
Address bit 15 0000003AH 0000003BH 00000038H 00000039H () R/W R X : Access : Readable and writable : Read only : Unused : Indeterminate ADCS ADCR bit 0
Initial value 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - - - - - - X XB X X X X X X X XB (R/W) (R)
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MB91121
9. Interrupt Controller
The interrupt controller processes interrupt acknowledgments and arbitration between interrupts. * Block diagram
INT0
2
IM
Priority judgment OR 5 NMI NMI processing 4 Level judgment RI00 * * * RI47 (DLYIRQ) DLYI
1
5
LEVEL4 to LEVEL0 4
ICR00 6 * * * * * ICR47 Vector judgment
Level vector generation
HLDREQ cancel request
HLDCAN
3
6
VCT5 to VCT0 5
R-bus
*1 : DLYI stands for delayed interrupt module (delayed interrupt generation block) (refer to the section "11. Delayed Interrupt Module" for detail) . *2 : INT0 is a wake-up signal to clock control block in the sleep or stop status. *3 : HLDCAN is a bus release request signal for bus masters other than CPU. *4 : LEVEL5 to LEVEL0 are interrupt level outputs. *5 : VCT5 to VCT0 are interrupt vector outputs.
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MB91121
* Register configuration
Address bit 7 00000400H 00000401H 00000402H 00000403H 00000404H 00000405H 00000406H 00000407H 00000408H 00000409H 0000040AH 0000040BH 0000040CH 0000040DH 0000040EH 0000040FH 00000410H ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 bit 0
Initial value - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Address bit 7 00000411H 00000412H 00000413H 00000414H 00000415H 00000416H 00000417H 00000418H 00000419H 0000041AH 0000041BH 0000041CH 0000041DH 0000041EH 0000041FH 0000042FH 00000431H 00000430H ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR47 HRCL DICR bit 0
Initial value - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - 1 1 1 1 1B - - - - - - - 0B (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
( ) : Access R/W : Readable and writable : Unused
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MB91121
10. External Interrupt/NMI Control Block
The external interrupt/NMI control block controls external interrupt request signals input to NMI pin and INT0 to INT3 pins. Detecting levels can be selected from "H", "L", rising edge and falling edge (not for NMI pin) . * Block diagram
8
Interrupt enable register
R-bus
Interrupt request
9
Gate
Cause F/F
Edge detection circuit
5
INT0 to INT7 NMI
8
Interrupt cause register
8
Request level setting register
* Register configuration
Address bit 15 00000095H 00000094H 00000099H ( ) : Access R/W : Readable and writable EIRR ELVR bit 8 ENIR bit 0
Initial value 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B (R/W) (R/W) (R/W)
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MB91121
11. Delayed Interrupt Module
Delayed interrupt module is a module which generates an interrupt for changing a task. By using this delayed interrupt module, an interrupt request to CPU can be generated/cancelled by the software. Refer to the section "9. Interrupt Controller" for delayed interrupt module block diagram. * Register configuration
Address bit 7 00000430H ( ) : Access R/W : Readable and writable : Unused DICR bit 0
Initial value - - - - - - - 0B (R/W)
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MB91121
12. Clock Generation (Low-power consumption mechanism)
The clock control block is a module which undertakes the following functions. * * * * * * CPU clock generation (including gear function) Peripheral clock generation (including gear function) Reset generation and cause hold Standby function (including hardware standby) DMA request prohibit PLL (multiplier circuit) embedded
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MB91121
* Block diagram
[Gear control block] Gear control register (GCR) CPU gear Peripheral gear R-bus PCTR register PLL 1/2 Selection circuit CPU clock Internal bus clock External bus clock Internal clock generation circuit Peripheral DMA clock DSP Macros clock Internal peripheral clock [Stop/sleep control block] Internal interrupt request Internal reset Standby control register (STCR) STOP state CPU hold enable HST pin Status transition control circuit Reset generation F/F [DMA prohibit circuit] DMA request DMA request prohibit register (PDRR) [Reset cause circuit] Power on sel SLEEP state CPU hold request Internal reset
X0 X1
Oscillator circuit
RST pin
Reset cause register (RSRR) [Watchdog control block] Watchdog reset generation postpone register (WPR) Watchdog reset postpone register Timebase timer clear register (CTBR) Timebase timer Count clock
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MB91121
* Register configuration
Address bit 15 00000480H 00000481H 00000482H 00000483H 00000484H 00000485H () R/W R X : Access : Readable and writable : Read only : Unused : Indeterminate GCR WPR PDRR CDBR RSRR/WTCR STCR bit 8 bit 0
Initial value 1 X X X X - 0 0B 0 0 0 1 1 1 - -B - - - - 0 0 0 0B X X X X X X X XB 1 1 0 0 1 1 - 1B X X X X X X X XB (R/W) (R/W) (R/W) (W) (R/W) (W)
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MB91121
13. External Bus Interface
The external bus interface controls the interface between the device and the external memory and also the external I/O, and has the following features. * 25-bit (32 Mbytes) address output * 6 independent banks owing to the chip select function. Can be set to anywhere on the logical address space for minimum unit 64 Kbytes. Total 32 Mbytes x 6 area setting is available by the address pin and the chip select pin. * 8/16-bit bus width setting are available for every chip select area. * Programmable automatic memory wait (Max. for 7 cycles) can be inserted. * DRAM interface support Three kinds of DRAM interface : Double CAS DRAM (normally DRAM I/F) Single CAS DRAM Hyper DRAM 2 banks independent control (RAS, CAS, etc. control signals) DRAM select is available from 2CAS/1WE and 1CAS/2WE. Hi-speed page mode supported CBR/self refresh supported Programmable wave form * Unused address/data pin can be used for I/O port. * Little endian mode supported * Clock doublure : Internal bus 50 MHz, external bus 25 MHz
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MB91121
* Block diagram
Address bus 32
Data bus 32
A-OUT External data bus Write buffer Switch MUX
Read buffer
Switch
DATA BLOCK ADDRESS BLOCK External address bus
+1 or +2 Inpage Address buffer Shifter 6 Comparator
ASR AMR
CS0 to CS5
DRAM control DMCR Underflow Refresh counter To TBT
8
RAS0, RAS1 CS0L, CS1L CS0H, CS1H DW0, DW1
3 External pin control block All blocks control 4 Registers & control
RD WR0, WR1 BRQ BGRNT CLK RDY
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MB91121
* Register configuration
Address bit 31 0000060CH 0000060DH 0000060EH 0000060FH 00000610H 00000611H 00000612H 00000613H 00000614H 00000615H 00000616H 00000617H 00000618H 00000619H 0000061AH 0000061BH 0000061CH 0000061DH 0000061EH 0000061FH 00000620H 00000621H 00000622H 00000623H 00000624H 00000625H 00000626H 00000627H 00000628H 00000629H 0000062BH 0000062CH 0000062DH 0000062EH 0000062FH 000007FEH 000007FFH ( ) : Access W : Write only X : Indeterminate DMCR4 DMCR5 LER MODR EPCR0 EPCR1 AMD5 DSCR RFCR AMD0 AMD1 AMD32 AMD4 ASR5 AMR5 ASR4 AMR4 ASR3 AMR3 ASR2 AMR2 ASR1 AMR1 bit 16 bit 0 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 1 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 1 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - - - 0 0 1 1 1B 0 - - 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 - - 0 0 0 0 0B 0 - - 0 0 0 0 0B 0 0 0 0 0 0 0 0B - - X X X X X XB 0 0 - - - 0 0 0B - - - 1 1 0 0 0B - 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 -B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 -B - - - - - 0 0 0B X X X X X X X XB (W) (W) (W) (W) (W) (W) (W) (W) (W) (W) (R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) (W) (W) (R/W) (R/W) (W) (W) Initial value
R/W : Readable and writable : Unused
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MB91121
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Power supply voltage Analog supply voltage Analog reference voltage Input voltage Analog pin input voltage Output voltage "L" level maximum output current "L" level average output current "L" level maximum total output current "L" level average total output current "H" level maximum output current "H" level average output current "H" level maximum total output current "H" level average total output current Power consumption Operating temperature Storage temperature Symbol VCC AVCC AVRH VI VIA VO IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD TA Tstg Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 0 -55 Max. VSS + 3.6 VSS + 3.6 VSS + 3.6 VCC + 0.3 AVCC + 0.3 VCC + 0.3 10 4 100 50 -10 -4 -50 -20 600 +70 +150 (VSS = AVSS = 0.0 V) Unit V V V V V V mA mA mA mA mA mA mA mA mW C C *4 *4 *2 *3 *2 *3 *1 *1 Remarks
*1 : Care must be taken that AVCC and AVRH do not exceed VCC + 0.3 V, such as when turning on the device. Also, care must be taken that AVRH does not exceed AVCC. *2 : Maximum output current is a peak current value measured at a corresponding pin. *3 : Average output current is an average current for a 100 ms period at a corresponding pin. *4 : Average total output current is an average current for a 100 ms period for all corresponding pins. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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MB91121
2. Recommended Operating Conditions
Parameter Power supply voltage Analog supply voltage Analog reference voltage Operating temperature Symbol VCC AVCC AVRH TA Value Min. 3.0 VSS + 0.3 AVSS 0 Max. 3.6 VSS + 3.6 AVCC +70
(VSS = AVSS = 0.0 V) Unit V V V C Remarks
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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MB91121
3. DC Characteristics
Parameter Symbol Pin name Input pin except for hysteresis input *1 Input pin except for hysteresis input *1
(VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 C to + 70 C) Condition Value Min. 0.65 x VCC Typ. Max. VCC + 0.3 Unit Remarks
"H" level input voltage
VIH
V
*2
VIHS
0.8 x VCC
VCC + 0.3
V
Hysteresis input*2
"L" level input voltage
VIL
VSS - 0.3
0.25 x VCC
V
*2
VILS "H" level output voltage "L" level output voltage Input leakage current (Hi-Z output leakage current) Pull-up resistance
VSS - 0.3 VCC - 0.5

0.2 x VCC
V
Hysteresis input*2
VOH
D16 to D31 VCC = 3.0 V A00 to A24 IOH = -4.0 mA P6 to PF D16 to D31 VCC = 3.0 V A00 to A24 IOL = 4.0 mA P6 to PF D00 to D31 VCC = 3.6 V A00 to A23 0.45 V< VI < VCC P8 to PF RST VCC = 3.6 V VI = 0.45 V FC = 12.5 MHz VCC = 3.3 V VCC FC = 12.5 MHz VCC = 3.3 V TA = +25 C VCC = 3.3 V Except for VCC, AVCC, AVSS, VSS
V
VOL
0.4
V
ILI
-5
+5
A
RPULL
25
50
100
k (4 multiplication) mA Operation at 50 MHz mA Sleep mode A Stop mode pF
ICC Power supply current
130
180
ICCS ICCH

85 15
120 150
Input capacitance
CIN
10
*1 : Hysteresis input pin : NMI, RST, P60 to P67, PA1 to PA6, PB0 to PB7, PE0 to PE7, PF0 to PF7, PG0 to PG7, PI0, PI1 *2 : VCC3 = 3.3 0.2 V (internal regulator output voltage) when using 5 V power supply, VCC3 = power supply voltage when using 3V power supply (internal regulator unused)
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MB91121
4. AC Characteristics
(1) Measurement Conditions The following conditions apply to AC characteristics unless otherwise specified. * Measurement conditions for AC standards VCC : 3.0 V to 3.6 V
Input VCC HIH VIL 0V VOH VOL Output
VIH
1/2 VCC
VOH
1/2 VCC
VIL 1/2 VCC VOL 1/2 VCC (The input rise/fall time is 10 ns or less.)
* Load condition
Output pin C = 50 pF (VCC : 3.0 V to 3.6 V)
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MB91121
(2) Clock Timing Rating
(VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 .0V, TA = 0 C to + 70 C) Symbol Pin name Condition FC tC f FC FC tC PWH, PWL tCR, tCF fCP fCPB fCPP tCP X0, X1 X0, X1 X0, X1 X0, X1 X0, X1 X0, X1 X0, X1 Value Min. 10 80 10 10 40 25 10 0.625*2 0.625*2 0.625* 20 40*3 40
2
Parameter Clock frequency (1) Clock cycle time Frequency shift ratio*1 (when locked) Clock frequency (2) Clock frequency (3) Clock cycle time Input clock pulse width Input clock rising/falling time Internal operating clock frequency
Max. 12.5 100 5 25 25 100 8 50 25*3 25 1600*
2
Unit MHz ns % MHz MHz ns ns ns ns MHz MHz MHz ns ns ns
Remarks
When using PLL
Self-oscillation (divide-by-2 input) External clock (divide-by-2 input) Input to X0 only Input to X0, X1 (tCR + tCF) CPU system Bus system Peripheral system CPU system Bus system Peripheral system
Internal operating clock cycle time
tCPB tCPP
1600*2 1600*2
*1 : Frequency shift ratio stands for deviation ratio of the operating clock from the center frequency in the clock multiplication system.
+
f =
|| x 100 (%) f0
+ Center frequency f0 - -
*2 : These values are for a minimum clock of 10 MHz input to X0, a divide-by-2 system of the source oscillation and a 1/8 gear. *3 : Values when using the doublure and CPU operation at 50 MHz.
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MB91121
* Clock timing rating measurement conditions
tC 0.8 VCC 0.2 VCC PWH tCF PWL tCR
* Guaranteed operating range
VCC (V)
Guaranteed operating range (T A = 0 C to +70 C) f CPP falls within the shaded range.
Power supply
3.6 3.0 3.3 V 0.3 V fCP / fCPP [MHz]
0
0.625
25 Internal clock
50
* External/internal clock setting range
Internal clock setting upper limit
fCP
50 40 CPU PLL system (4 multiplication)
fCPP
25 20 12.5 5 0 0
Peripheral
Divide-by-2 system
10 12.5
25 External clock Internal oscillation
50
FC [MHz]
Oscillation input clock
Note : 1.If the PLL is used, the external clock input should be 10.0 MHz to 12.5 MHz. 2.The PLL oscillation settling time must be longer than 300 s. 3.The internal clock gear setting must fall within the above range.
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MB91121
(3) Clock Output Timing Pin name CLK CLK CLK CLK CLK tCHCL tCLCH CLK CLK
(VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 C to + 70 C) Condition Value Min. tCP Max. -- -- 1 / 2 x tCYC + 10 1 / 2 x tCYC + 10 ns ns ns Unit Remarks *1 Using the doublure *2 *3
Parameter
Symbol
Cycle time
tCYC
tCPB 1 / 2 x tCYC - 10 1 / 2 x tCYC - 10
tCYC tCHCL tCLCH VOH VOL
CLK
VOH
*1 : tCYC is a frequency for 1 clock cycle including a gear cycle. Use the doublure when CPU frequency is above 25 MHz. *2 : Rating at a gear cycle of x 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equations with 1/2, 1/4, 1/8, respectively. Min. : (1 - n / 2) x tCYC - 10 Max. : (1 - n / 2) x tCYC + 10 Select a gear cycle of x 1 when using the doublure. *3 : Rating at a gear cycle of x 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equations with 1/2, 1/4, 1/8, respectively. Min. : n / 2 x tCYC - 10 Max. : n / 2 x tCYC + 10 Select a gear cycle of x 1 when using the doublure.
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MB91121
The relation between source oscillation input and CLK pin for configured by CHC/CCK1/CCK0 settings of GCR (gear control register) is as follows: However, in this chart source oscillation input means X0 input clock.
Source oscillation input (when using the doublure) (1) PLL system (CHC bit of GCR set to "0") (a) Gear x 1 CLK pin CCK1/0: "00" tCYC tCYC
Source oscillation input (2) 2 dividing system (CHC bit of GCR set to "1") (a) Gear x 1 CLK pin CCK1/0: "00" (b) Gear x 1/2 CLK pin CCK1/0: "01" (c) Gear x 1/4 CLK pin CCK1/0: "10" (d) Gear x 1/8 CLK pin CCK1/0: "11" tCYC
tCYC
tCYC
tCYC
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MB91121
* Ceramc oscillator applications
Recommended circuit (2 contacts)
Recommended circuit (3 contacts)
X0 *
X1
X0 *
X1
C1
C2
C1
C2
C1, C2 internally connected.
* : Murata Mfg. Co., Ltd.
* Discrete type Oscillation frequency [MHz] 10.00 to 13.00 13.01 to 15.99 16.00 to 19.99 20.00 to 25.00 CSA CST CSA CST CSA CSA Model name MTZ MTW MXZ040 MXW0C3 MXZ040 MXZ004 Circuit constants C1[pF] 30 (30) 15 (15) (10) None C1[pF] 30 (30) 15 (15) (10) None Rf[]*1 Rd[]*2 0 0 0 0 0 0 Pin type Two-pin Three-pin Two-pin Three-pin Two-pin Three-pin Two-pin Three-pin

*1 : Feedback resistor Rf is built in the LSI. *2 : No dumping resistor is required. ( ) : C1 and C2 integrated
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MB91121
* SMD type Oscillation frequency [MHz] 10.00 to 13.00 13.01 to 15.99 16.00 to 19.99 20.00 to 25.00 Model name CSACS CSTCS CSACS CSTCS CSACS CSTCS CSACS MT MT MX040 MX0C3 MX040 MX0C2 MX040 Circuit constants C1[pF] 30 (30) 15 (15) 10 (10) None C1[pF] 30 (30) 15 (15) 10 (10) None Rf[]*1 Rd[]*2 0 0 0 0 0 0 0 Pin type Two-pin Three-pin Two-pin Three-pin Two-pin Three-pin Two-pin Three-pin
*1 : Feedback resistor Rf is built in the LSI. *2 : No dumping resistor is required. ( ) : C1 and C2 integrated
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MB91121
(4) Reset input ratings Pin name RST
(VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 C to + 70 C) Condition Value Min. tCP x 5 Max. Unit ns Remarks
Parameter Reset input time
Symbol tRSTL
tRSTL, tHSTL
RST
0.2 VCC
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MB91121
(5) Power-on Reset Pin name
(VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 C to + 70 C) Symbol Condition Value Min. 50 s Max. Unit Remarks VCC < 0.2 V before the power supply rising Repeated operations
Parameter
Power supply rising time
tR
VCC
VCC = 3.3 V
18
ms
Power supply shut off time
tOFF
VCC
1
ms
tR
VCC
0.9 x VCC 0.2 V tOFF
Note: Sudden change in supply voltage during operation may initiate a power-on sequence. To change supply voltage during operation, it is recommended to smoothly raise the voltage to avoid rapid fluctuations in the supply voltage.
VCC
A voltage rising rate of 50 mV/ms or less is recommended.
VSS
Note: Set RST pin to OLO level when turning on the device, at least the described above duration after the supply voltage reaches Vcc is necessary before turning the RST to OHO level.
VCC
RST
tRSTL
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MB91121
(6) Normal Bus Access Read/write Operation
(VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 C to + 70 C) Condition Value Min. Max. 15 15 15 15 10 10 10 10 3 / 2 x tCYC - 40 tCYC - 25 Unit Remarks ns ns ns ns ns ns ns ns ns ns ns ns *1 *2 *1
Parameter CS0 to CS5 delay time Address delay time Data delay time RD delay time WR0, WR1 delay time Valid address valid data input time RD valid data input time Data set up RD time RD data hold time
Symbol tCHCSL tCHCSH tCHAV tCHDV tCLRL tCLRH tCLWL tCLWH tAVDV tRLDV tDSRH tRHDX
Pin name CLK CS0 to CS5 CLK A24 to A00 CLK D31 to D16 CLK RD CLK WR0, WR1 A24 to A00 D31 to D16
RD D31 to D16
25 0
*1 : When bus timing is delayed by automatic wait insertion or RDY input, add (tCYC x extended cycle number for delay) to this rating. *2 : Rating at a gear cycle of x 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equation with 1/2, 1/4, 1/8, respectively. Equation : (2 - n / 2) x tCYC - 40
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MB91121
tCYC BA1 BA2 VOH VOH
CLK
VOH
VOL
VOL
tCHCSL
tCHCSH VOH
CS0 to CS5
VOL
tCHAV
A24 to A00
VOH VOL
VOH VOL
tCLRL
tCLRH VOH
RD
VOL tRLDV
tRHDX tAVDV
D31 to D16
VIH VIL
Read
VIH VIL tDSRH
tCLWL
tCLWH VOH
WR0 , WR1
VOL
tCHDV
D31 to D16
VOH VOL
Write
VOH VOL
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MB91121
(7) Ready Input Timing
(VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 C to + 70 C) Symbol tRDYS tRDYH Pin name RDY CLK CLK RDY Condition Value Min. 20 0 ns Max. Unit ns Remarks
Parameter RDY set up time CLK CLK RDY hold time
tCYC
CLK
VOH
VOL
VOH tRDYH tRDYS
VOL tRDYH tRDYS
RDY When wait(s) is inserted.
VIL
VIH
RDY When no wait is inserted.
VIH
VIL
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MB91121
(8) Hold Timing
(VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 C to + 70 C) Symbol tCHBGL tCHBGH tXHAL tHAHV Pin name CLK BGRNT BGRNT Condition Value Min. tCYC - 10 tCYC - 10 Max. 10 10 tCYC + 10 tCYC + 10 Unit ns ns ns ns Remarks
Parameter BGRNT delay time Pin floating BGRNT time BGRNT pin valid time
Note : There is a delay time of more than 1 cycle from BRQ input to BGRNT change.
tCYC
CLK
VOH
VOH
VOH
VOH
BRQ
tCHBGL VOH
tCHBGH
BGRNT
tXHAL
VOL
tHAHV
Each pin
High impedance
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MB91121
(9) Normal DRAM Mode Read/Write Cycle
(VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 C to + 70 C) Condition Value Min. 0 Max. 10 10 10 10 15 15 15 15 15 5 / 2 x tCYC - 20 tCYC - 17 Unit ns ns ns ns ns ns ns ns ns ns ns ns *1 *2 *1 Remarks
Parameter RAS delay time CAS delay time ROW address delay time COLUMN address delay time DW delay time Output data delay time RAS valid data input time CAS valid data input time CAS data hold time
Symbol tCLRAH tCHRAL tCLCASL tCLCASH tCHRAV tCHCAV tCHDWL tCHDWH tCHDV1 tRLDV tCLDV tCADH
Pin name CLK RAS CLK CAS CLK A24 to A00 CLK DW CLK D31 to D16 RAS D31 to D16 CAS D31 to D16
*1 : When Q1 cycle or Q4 cycle is extended for 1 cycle, add tCYC time to this rating. *2 : Rating at a gear cycle of x 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equation with 1/2, 1/4, 1/8, respectively. Equation : (3 - n / 2) x tCYC - 20
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MB91121
tCYC Q1 Q2 VOL Q3 VOH VOL VOL Q4 Q5 VOH
CLK
VOH
RAS
tCLRAH
VOH
VOL tCHRAL tCLCASL tCLCASH VOH
CAS
VOL
tCHRAV
tCHCAV ROW address VOH VOL VOH VOL tRLDV tCLDV tCADH Read VIH VIL COLUMN address VOH VOL
A24 to A00
VOH VOL
D31 to D16
VIH VIL
DW
VOH VOL tCHDWL tCHDWH
D31 to D16
VOH VOL tCHDV1
Write
VOH VOL
78
MB91121
(10) Normal DRAM Mode Fast Page Read/Write Cycle (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 C to + 70 C) Parameter RAS delay time CAS delay time COLUMN address delay time DW delay time Output data delay time CAS valid data input time CAS data hold time Symbol tCLRAH tCLCASL tCLCASH tCHCAV tCHDWH tCHDV1 tCLDV tCADH Pin name CLK, RAS CLK CAS CLK A24 to A00 CLK, DW CLK D31 to D16 CAS D31 to D16 Condition Value Min. 0 Max. 10 10 10 15 15 15 tCYC - 17 Unit ns ns ns ns ns ns ns ns * Remarks
* : When Q4 cycle is extended for 1 cycle, add tCYC time to this rating.
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MB91121
Q5
Q4 VOH VOL
Q5 VOL
Q4
Q5 VOH VOL
CLK
tCLRAH
RAS
VOH
tCLCASL
tCLCASH VOH
CAS
VOL
tCHCAV
A24 to A00
COLUMN address
VOH VOL
COLUMN address
VOH VOL
COLUMN address
tCLDV VIH VIL
tCADH VIH VIL
D31 to D16
Read
Read
Read
tCHDWH
DW
VOH
tCHDV1
D31 to D16
VOH VOL
Write
VOH VOL
VOH VOL
Write
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MB91121
(11) Single DRAM Timing
(VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 C to + 70 C) Symbol tCLRAH2 tCHRAL2 Pin name CLK RAS Condition Value Min. 0 Max. 10 10 n / 2 x tCYC +8 10 15 15 15 15 15 (1 - n / 2) x tCYC - 17 -- Unit ns ns ns ns ns ns ns ns ns ns ns Remarks
Parameter RAS delay time
CAS delay time ROW address delay time COLUMN address delay time DW delay time Output data delay time CAS Valid data input time CAS data hold time
tCHCASL2 CLK CAS tCHCASH2 tCHRAV2 tCHCAV2 tCHDWL2 CLK A24 to A00
CLK tCHDWH2 DW tCHDV2 tCLDV2 tCADH2 CLK D31 to D16 CAS D31 to D16
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MB91121
tCYC Q1 Q2 VOL Q3 VOH VOH
*1 Q4S VOH
Q4S VOH
Q4S VOH
CLK
RAS
VOH tCLRAH2
VOL tCHRAL2 tCHCASL2 tCHCASH2
CAS
VOH VOL VOL
VOH
A24 to A00
VOH VOL
ROW address
VOH VOL
VOHCOLUMN-0 VOL tCHCAV2
COLUMN-1
COLUMN-2
tCHRAV2
tCADH2 tCLDV2 VIH VIL VIH VIL
D31 to D16
Read-0
Read-1
Read-2
DW
VOL tCHDWL2 *2 VOH VOL tCHDV2 tCHDWH2
VOH
D31 to D16
VOH VOL tCHDV2
Write-0
VOH VOL
Write-1 VOH VOH VOL VOL
Write-2
*1 : Q4S indicates Q4SR (Read) of Single DRAM cycle or Q4SW (Write) cycle. *2 : indicates the timing when the bus cycle begins from the high speed page mode.
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MB91121
(12) Hyper DRAM Timing
(VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 C to + 70 C) Symbol tCLRAH3 tCHRAL3 Pin name CLK RAS Condition Value Min. CLK RD 0 Max. 10 10 n / 2 x tCYC + 8 10 15 15 15 15 15 15 15 15 tCYC - 20 Unit Remarks ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Parameter RAS delay time CAS delay time ROW address delay time COLUMN address delay time RD delay time
tCHCASL3 CLK tCHCASH3 CAS tCHRAV3 tCHCAV3 tCHRL3 tCHRH3 tCLRL3 tCHDWL3 CLK A24 to A00
DW delay time Output data delay time CAS valid data input time CAS data hold time
CLK tCHDWH3 DW tCHDV3 tCLDV3 tCADH3 CLK D31 to D16 CAS D31 to D16
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MB91121
tCYC Q1 Q2 VOL Q3 VOH VOH
*1 Q4H VOH VOL
Q4H VOH
Q4H VOH
CLK
RAS
VOH tCLRAH3
VOL tCHRAL3 tCHCASL3 tCHCASH3
CAS
VOH VOL VOL VOL
A24 to A00
VOH VOL
ROW address
VOH VOL
VOHCOLUMN-0 VOL tCHCAV3
COLUMN-1
COLUMN-2
tCHRAV3
*2
RD
VOL tCHRL3
VOL tCLRL3 tCLDV3 Read-0 VIH VIL tCHRH3
VOH
tCADH3 VIH Read-1 VIL
D31 to D16
DW
VOL tCHDWL3 tCHDWH3
VOH
*2
D31 to D16
VOH VOL tCHDV3
Write-0
VOH VOL tCHDV3
VOH VOL
Write-1 VOH VOH VOL VOL
Write-2
*1 : Q4H indicates Q4HR (Read) of Hyper DRAM cycle or Q4HW (Write) cycle. *2 : indicates the timing when the bus cycle begins from the high speed page mode.
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MB91121
(13) CBR Refresh
(VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 C to + 70 C) Symbol tCLRAH tCHRAL tCLCASL tCLCASH Pin name CLK RAS CLK CAS Condition Value Min. Max. 10 10 10 10 Unit ns ns ns ns Remarks
Parameter RAS delay time CAS delay time
tCYC R1
R2 VOH VOL
R3
R4 VOL
CLK
VOH VOL
RAS
VOH tCLRAH
VOL tCHRAL
CAS
VOL tCLCASL
VOH tCLCASH
DW
85
MB91121
(14) Self Refresh
(VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 C to + 70 C) Symbol tCLRAH tCHRAL tCLCASL tCLCASH Pin name CLK RAS CLK CAS Condition Value Min. Max. 10 10 10 10 Unit ns ns ns ns Remarks
Parameter RAS delay time CAS delay time
tCYC SR1
SR2 VOH VOL VOH
SR3
SR3 VOL
CLK
VOH
tCHRAL
tCLRAH VOH
RAS
VOL
CAS
VOL tCHCASL
VOH tCLCASH
86
MB91121
(15) UART Timing
(VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 C to + 70 C) Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name SC0 to SC2 SC0 to SC2 SO0 to SO2 Internal SC0 to SC2 shift clock mode SI0 to SI2 SC0 to SC2 SI0 to SI2 SC0 to SC2 SC0 to SC2 SC0 to SC2 SO0 to SO2 External shift clock SC0 to SC2 mode SI0 to SI2 SC0 to SC2 SI0 to SI2 Condition Value Min. 8tCYCP -80 100 60 4tCYCP 4tCYCP 60 60 Max. 80 150 Unit ns ns ns ns ns ns ns ns ns Remarks
Parameter Serial clock cycle time SCLK SOUT delay time Valid SIN SCLK SCLK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCLK SOUT delay time Valid SIN SCLK SCLK valid SIN hold time
Note : This rating is for AC characteristics in CLK synchronous mode. tCYCP is a cycle time of peripheral system clock * Internal shift clock mode
tSCYC VOH VOL tSLOV VOH VOL tIVSH tSHIX VIH VIL VOL
SCLK
SOUT
SIN
VIH VIL
* External shift clock mode
tSLSH tSHSL VIH VIL tSLOV VOH VOL tIVSH tSHIX VIH VIL VIL VIH
SCLK
SOUT
SIN
VIH VIL
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MB91121
(16) Trigger System Input Timing
(VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 C to + 70 C) Pin name ATG TRG0 to TRG3 Condition Value Min. 5tCYCP Max. Unit ns Remarks
Parameter A/D start trigger input time External interrupt input time
Symbol tTRGH tTRGL
Note : tCYCP is a cycle time of peripheral system clock
tTRGH
tTRGL VIH VIL VIL
ATG TRG0 to TRG3
VIH
88
MB91121
(17) DMA Controller Timing
(VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 C to + 70 C) Pin name DREQ0 to DREQ2 CLK DACK0 to DACK2 CLK EOP0 to EOP2 CLK DACK0 to DACK2 CLK EOP0 to EOP2 Condition Value Min. 2tCYC Max. 6 6 6 6 n / 2 x tCYC 6 n / 2 x tCYC 6 Unit ns ns ns ns ns ns ns ns ns Remarks
Parameter DREQ input pulse width DACK delay time (Normal bus) (Normal DRAM) EOP delay time (Normal bus) (Normal DRAM) DACK delay time (Single DRAM) (Hyper DRAM) EOP delay time (Single DRAM) (Hyper DRAM)
Symbol tDRWH tCLDL tCLDH tCLEL tCLEH tCHDL tCHDH tCHEL tCHEH
tCYC
CLK
VOH
VOL
VOH
VOL
DACK0 to DACK2 EOP0 to EOP2 (Normal bus) (Normal DRAM) DACK0 to DACK2 EOP0 to EOP2 (Single DRAM) (Hyper DRAM)
tCHDL tCHEL
tCLDL tCLEL VOL VOH
tCLDH tCLEH
VOL
VOH
tCHDH
tDRWH
DREQ0 to DREQ2
VIH
VIH
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MB91121
5. A/D Converter Block Electrical Characteristics
Parameter Resolution Total error Linearity error Differentiation linearity error Zero transition voltage Full-scale transition voltage Conversion time Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supply current Conversion variance between channels *1 : Machine clock = 25 MHz *2 : Current value for A/D converters not in operation, CPU stop mode (VCC = AVCC = AVRH = 3.3 V) Note : * As the absolute value of AVRH decreases, relative error increases. * Output impedance of external circuit of analog input under following conditions; Output impedance of external circuit < 5 k If output impedance of external circuit is too high, analog voltage sampling time may be too short for accurate sampling. Analog input circuit example Symbol VOT VFST IAIN VAIN IA IAH IR IRH
(VCC = AVCC = AVRH = 3.3 V, AVSS = 0.0 V, TA = 0 C to + 70 C) Pin name AN0 to AN7 AN0 to AN7 AN0 to AN7 AVRH AVCC AVRH AN0 to AN7 Value Min. -1.5 5.6*1 AVSS AVSS Typ. 10 +0.5 0.1 4 200 Max. 10 5.0 3.5 2.0 +2.5 10 AVRH AVCC 5*
2
Unit BIT LSB LSB LSB LSB s A V V mA A A A LSB
AN0 to AN7 AVRH - 4.5 AVRH - 1.5 AVRH + 0.5 LSB
5*2 5
Sample-and-hold circuit Analog input C0 Comparator RON1 RON1 : 0. 2 k RON2 : 1. 4 k RON3 : 1. 4 k RON4 : 0. 2 k RON2 RON3 RON4 C1
C0 : 16.6 pF C1 : 4.0 pF
Note : These values are given for reference purposes.
90
MB91121
6. A/D Converter Glossary
* Resolution The smallest change in analog voltage detected by A/D converter. * Linearity error A deviation of actual conversion characteristic from a line connecting the zero-traction point (between "00 0000 0000" "00 0000 0001") to the full-scale transition point (between "11 1111 1110" "11 1111 1111") . * Differential linearity error A deviation of a step voltage for changing the LSB of output code from ideal input voltage.
Linearity error 3FF 3FE {1 LSB x (N - 1) + VOT} 3FD Digital output VFST (measured value) 004 003 002 Ideal characteristic 001 VOT (measured value) AVRL AVRH AVRL N-2 VNT (measured value) Actual conversion characteristic Digital output N
Differential linearity error
Actual conversion characteristic N+1 Actual conversion characteristic
Ideal characteristic
N-1 V(N + 1)T VNT (measured value) (measured value) Actual conversion characteristic Analog input AVRH
Analog input
Linearity error of digital output N =
VNT - {1 LSB x (N - 1) + VOT} 1 LSB V(N + 1)T - VNT 1 LSB VFST - VOT 1022 -1
[LSB]
Differential linearity error of digital output N =
[LSB]
1 LSB =
[V]
VOT: A voltage for causing transition of digital output from (000)H to (001)H VFST: A voltage for causing transition of digital output from (3FE)H to (3FF)H VNT: A voltage for causing transition of digital output from (N - 1)H to N
91
MB91121
* Total error A difference between actual value and theoretical value. The overall error includes zero-transition error, fullscale transition error and linearity error.
Total error 3FF 1.5 LSB 3FE 3FD Digital output {1 LSB x (N - 1) + 0.5 LSB} Actual conversion characteristic
004 003 002 001 0.5 LSB AVRL Analog input AVRH VNT (measured value) Actual conversion characteristic Ideal characteristic
Total error of digital output N =
VNT - {1 LSB x (N - 1) + 0.5 LSB} 1 LSB
[LSB]
1 LSB (ideal value) =
AVRH - AVRL 1024
[V]
VOT VFST
(ideal value) = AVRL + 0.5 LSB [V] (ideal value) = AVRL - 1.5 LSB [V]
VNT: A voltage for causing transition of digital output from (N - 1) to N
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MB91121
s EXAMPLE CHARACTERISTICS
(1) Power Supply Current Power supply current-Power supply voltage
160 140 120 ICCS (mA) 100 ICC (mA) 80 60 40 20 0 2.7 20 0 2.7 25 MHz 50 MHz 80 60 40 25 MHz 50 MHz
Power supply current (sleeping) -Power supply voltage
120 100
3
3.3 VCC (V)
3.6
3.9
3
3.3 VCC (V)
3.6
3.9
Power supply current (stopping) -Power supply voltage
100 90 80 70 ICCH (mA) 60 50 40 30 20 10 0 -10 2.7 3 3.3 VCC (V) 3.6 3.9
A/D power supply current-Power supply voltage
100 90 80 70 60 IA (mA) 50 40 30 20 10 0 -10 2.7 3 3.3 VCC (V) 3.6 3.9
50 MHz
50 MHz
A/D reference power supply current -Power supply voltage
180 160 140 120 IR (mA) 100 50 MHz 80 60 40 20 0 2.7 3 3.3 VCC (V) 3.6 3.9
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MB91121
(2) Output Voltage "H" output voltage-Power supply voltage
4 3.8 3.6 3.4 VOL (mV) VOH (V) 3.2 3 2.8 2.6 2.4 2.2 2 2.7 3 3.3 VCC (V) 3.6 3.9 60 2.7 3 3.3 VCC (V) 3.6 3.9 90 100
"L" output voltage-Power supply voltage
80
70
(3) Pull-up Resistance Pull-up resistance-Power supply voltage
100
R (k) 10 2.7 3 3.3 VCC (V) 3.6 3.9
94
MB91121
s ORDERING INFORMATION
Part number MB91121PFV Package 120-pin Plastic LQFP (FPT-120P-M21) Remarks
95
MB91121
s PACKAGE DIMENSION
120-pin plastic LQFP (FPT-120P-M21)
18.000.20(.709.008)SQ 16.000.10(.630.004)SQ
90 61
91
60
0.08(.003)
Details of "A" part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
INDEX
0~8
120 31
"A" 0.100.05 (.004.002) (Stand off) 0.25(.010)
LEAD No.
1
30
0.50(.020)
0.220.05 (.009.002)
0.08(.003)
M
0.145 -0.03 .006 -.001
+0.05 +.002
0.600.15 (.024.006)
C
2001 FUJITSU LIMITED F120033S-c-3-3
Dimensions in mm (inches)
96
MB91121
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0111 (c) FUJITSU LIMITED Printed in Japan

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